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dsPIC30F
6.3
Traps
Many of these trap conditions can only be detected
Traps can be considered as non-maskable, nestable
interrupts that adhere to a fixed priority structure.
Traps are intended to provide the user a means to
correct erroneous operation during debug and when
operating within the application. If the user does not
intend to take corrective action in the event of a trap
error condition, these vectors must be loaded with the
address of a software routine that will reset the device.
Otherwise, the trap vector is programmed with the
address of a service routine that will correct the trap
condition.
when they happen. Consequently, the instruction that
caused the trap is allowed to complete before
exception processing begins. Therefore, the user may
have to correct the action of the instruction that
caused the trap.
Each trap source has a fixed priority as defined by its
position in the IVT. An oscillator failure trap has the
highest priority, while an arithmetic error trap has the
lowest priority.
Table 6-2 contains information about the trap vector.
The dsPIC30F has four implemented sources of
6.4
Generating a Software Interrupt
non-maskable traps:
Any available interrupt can be manually generated by
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?
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Oscillator Failure Trap
Address Error Trap
Stack Error Trap
Arithmetic Error Trap
user software (even if the corresponding peripheral is
disabled), simply by enabling the interrupt and then
setting the interrupt flag bit when required.
TABLE 6-2:
TRAP VECTORS
Vector Number
0
1
2
3
4
5
6
7
DS70043F-page 18
IVT Address
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
AIVT Address
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
Trap Source
Reserved
Oscillator Failure
Address Error
Stack Error
Arithmetic Error
Reserved
Reserved
Reserved
? 2005 Microchip Technology Inc.
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